1. Field of the Invention
The present invention relates generally to dynamic logic in computers and, more particularly, to systems and methods for mitigating the effects of charge sharing in dynamic logic circuits, for example, mousetrap logic circuits.
2. Related Art
The central processing unit (CPU) in a computer must be designed to be extremely fast because it generally handles and ultimately supervises most of the interactions which occur within the computer. A critical factor which affects the speed at which a CPU can process data is the rate at which its arithmetic logic unit (ALU) can perform mathematical operations, such as addition, multiplication, and floating point manipulations. Typically, these mathematical operations are implemented via dedicated logic circuits within the CPU. These dedicated logic circuits must be fast, due to their frequent usage, so as not to undesirably slow the overall operation of and interaction with the CPU. Moreover, these dedicated logic circuits must be small in size so as to minimize the overall size of the CPU.
Traditionally, "static" logic gates have been utilized to construct logic circuits for performing mathematical operations. Static logic gates are those which can continuously perform logic operations so long as electrical power is available. In other words, static logic gates need no electrical precharge, or refresh, in order to properly perform logic operations. Static logic gates are functionally complete. They can directly perform both inverting and non-inverting functions. Further, they can be chained together, or cascaded, in several stages to collectively perform logic functions. However, static logic gates are undesirably slow individually and, when chained together to collectively perform a logic function, are even slower.
To achieve greater speed, "dynamic" logic gates were developed. Dynamic logic gates are those which require a periodic electrical precharge, or refresh, such as with a dynamic random access memory (DRAM), in order to maintain and properly perform its intended logic function. Once an electrical precharge supplied to a dynamic logic gate has been discharged by the dynamic logic gate, the dynamic logic gate can no longer perform another logic function until subsequently precharged again.
However, the use of conventional dynamic logic circuits in the construction of logic networks is problematic. Dynamic logic gates can be unreliable as a result of a "charge sharing" phenomenon. Charge sharing is a phenomenon which occurs after a node within the dynamic logic gate has been precharged. Essentially, the node acts as a storage capacitance (C.sub.s). As logic evaluations are performed in the dynamic logic gate, the precharge on the node may be "shared" with other nodes as a result of gate switching in the logic. The other nodes act as parasitic capacitances (C.sub.p), depleting the precharge. As a result, the precharge may be substantially diminished and thereby cause the dynamic logic gate to convey erroneous results or otherwise malfunction.